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msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 msp430g2x53 automotive mixed-signal microcontrollers 1 features ? package options ? tssop: 20 pin or 28 pin 1 ? qualified for automotive applications ? for complete module descriptions, see the ? low supply-voltage range: 1.8 v to 3.6 v msp430x2xx family user ? s guide ( slau144 ) ? ultra-low-power consumption ? active mode: 230 a at 1 mhz, 2.2 v 2 applications ? standby mode: 0.5 a ? power management ? off mode (ram retention): 0.1 a ? sensor interface ? five power-saving modes ? capacitive touch ? ultra-fast wakeup from standby mode in less than 1 s 3 description ? 16-bit risc architecture, 62.5-ns instruction the texas instruments msp430 ? family of ultra-low- cycle time power microcontrollers consists of several devices featuring different sets of peripherals targeted for ? basic clock module configurations various applications. the architecture, combined with ? internal frequencies up to 16 mhz with four five low-power modes, is optimized to achieve calibrated frequency extended battery life in portable measurement ? internal very-low-power low-frequency (lf) applications. the device features a powerful 16-bit oscillator risc cpu, 16-bit registers, and constant generators that contribute to maximum code efficiency. the ? 32-khz crystal digitally controlled oscillator (dco) allows the device ? external digital clock source to wake up from low-power modes to active mode in ? two 16-bit timer_a with three capture/compare less than 1 s. registers the msp430g2x53 series are ultra-low-power mixed ? up to 24 capacitive-touch enabled i/o pins signal microcontrollers with built-in 16-bit timers, up to ? universal serial communication interface (usci) 24 i/o capacitive-touch enabled pins, a versatile analog comparator, a 10-bit analog-to-digital (a/d) ? enhanced uart supports automatic baud- converter, and built-in communication capability using rate detection (lin) the universal serial communication interface. for ? irda encoder and decoder configuration details, see table 1 . ? synchronous spi typical applications include low-cost sensor systems ? i 2 c that capture analog signals, convert them to digital ? on-chip comparator for analog signal compare values, and then process the data for display or for transmission to a host system. function or slope analog-to-digital (a/d) conversion device information (1) ? 10-bit 200-ksps analog-to-digital converter (adc) package with internal reference, sample-and-hold, and order number body size (pin) autoscan msp430g2553ipw8rq1 pw (28) 9.7 mm x 4.4 mm ? brownout detector msp430g2553ipw0rq1 pw (20) 6.5 mm x 4.4 mm ? serial onboard programming, no external programming voltage needed, programmable code protection by security fuse ? on-chip emulation logic with spy-bi-wire (1) for the most current part, package, and ordering information, interface see the package option addendum at the end of this ? family members are summarized in table 1 document, or see the ti web site at www.ti.com . 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. productfolder sample &buy technical documents tools & software support &community
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 4 functional block diagram note: port p3 is available on 28-pin devices only. figure 1. functional block diagram, msp430g2x53 2 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1 clock system brownout protection rst/nmi dvcc dvss mclk watchdog wdt+ 15-bit timer0_a3 3 cc registers 16-mhz cpu includes 16 registers emulation 2bp jtag interface smclk aclk mdb mab port p1 8 i/o interrupt capability, pullup or pulldown resistors p1.x 8 p2.x port p2 8 i/o interrupt capability, pullup or pulldown resistors spy-bi- wire comp_a+ 8 channels timer1_a3 3 cc registers xin xout port p3 8 i/o pullup or pulldown resistors p3.x 8 8 ram 512b flash 16kb 8kb usci a0 uart, lin, irda, spi usci b0 spi, i2c adc 10-bit 8 ch. autoscan 1 ch dma
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 table of contents 9.20 internal very-low-power low-frequency oscillator 1 features ................................................................. 1 (vlo) ...................................................................... 33 2 applications .......................................................... 1 9.21 timer_a ................................................................ 33 3 description ............................................................ 1 9.22 usci (uart mode) ............................................. 34 4 functional block diagram ................................... 2 9.23 usci (spi master mode) ..................................... 34 5 revision history ................................................... 3 9.24 usci (spi slave mode) ....................................... 35 6 device characteristics ......................................... 4 9.25 usci (i 2 c mode) .................................................. 36 7 terminal configuration and functions ............... 5 9.26 comparator_a+ .................................................... 36 7.1 20-pin pw package (top view) .............................. 5 9.27 typical characteristics ? comparator_a+ ........... 37 7.2 28-pin pw package (top view) .............................. 5 9.28 10-bit adc, power supply and input range conditions ............................................................... 38 7.3 terminal functions .................................................. 6 9.29 10-bit adc, built-in voltage reference ............... 39 8 detailed description ............................................. 9 9.30 10-bit adc, external reference .......................... 40 8.1 cpu .......................................................................... 9 9.31 10-bit adc, timing parameters ........................... 40 8.2 instruction set .......................................................... 9 9.32 10-bit adc, linearity parameters ........................ 40 8.3 operating modes ................................................... 10 9.33 10-bit adc, temperature sensor and built-in v mid 8.4 interrupt vector addresses .................................... 11 ................................................................................. 41 8.5 special function registers (sfrs) ........................ 12 9.34 flash memory ...................................................... 41 8.6 memory organization ............................................. 13 9.35 ram ..................................................................... 42 8.7 bootstrap loader (bsl) ......................................... 13 9.36 jtag and spy-bi-wire interface .......................... 42 8.8 flash memory ........................................................ 13 9.37 jtag fuse ........................................................... 42 8.9 peripherals ............................................................. 14 10 i/o port schematics ........................................... 43 9 specifications ...................................................... 21 10.1 port p1 pin schematic: p1.0 to p1.2, input/output 9.1 absolute maximum ratings ................................... 21 with schmitt trigger ............................................... 43 9.2 recommended operating conditions .................... 21 10.2 port p1 pin schematic: p1.3, input/output with 9.3 active mode supply current into v cc excluding schmitt trigger ........................................................ 45 external current ...................................................... 22 10.3 port p1 pin schematic: p1.4, input/output with 9.4 typical characteristics, active mode supply current schmitt trigger ........................................................ 47 (into v cc ) ................................................................ 22 10.4 port p1 pin schematic: p1.5 to p1.7, input/output 9.5 low-power mode supply currents (into v cc ) with schmitt trigger ............................................... 49 excluding external current ..................................... 23 10.5 port p2 pin schematic: p2.0 to p2.5, input/output 9.6 typical characteristics, low-power mode supply with schmitt trigger ............................................... 51 currents .................................................................. 24 10.6 port p2 pin schematic: p2.6, input/output with 9.7 schmitt-trigger inputs, ports px ............................ 25 schmitt trigger ........................................................ 53 9.8 leakage current, ports px ..................................... 25 10.7 port p2 pin schematic: p2.7, input/output with 9.9 outputs, ports px ................................................... 25 schmitt trigger ........................................................ 55 9.10 output frequency, ports px ................................. 25 10.8 port p3 pin schematic: p3.0 to p3.7, input/output with schmitt trigger (28-pin pw and 32-pin rhb 9.11 typical characteristics, outputs .......................... 26 packages only) ....................................................... 57 9.12 pin-oscillator frequency ? ports px .................... 27 11 device and documentation support ................ 59 9.13 typical characteristics, pin-oscillator frequency ................................................................................. 27 11.1 device support .................................................... 59 9.14 por, bor ........................................................... 28 11.2 documentation support ....................................... 62 9.15 dco frequency ................................................... 30 11.3 related links ....................................................... 62 9.16 calibrated dco frequencies, tolerance ............. 31 11.4 community resources ......................................... 62 9.17 wakeup from lower-power modes (lpm3 or 11.5 trademarks .......................................................... 62 lpm4) ..................................................................... 32 11.6 electrostatic discharge caution ........................... 62 9.18 typical characteristics, dco clock wakeup time 11.7 glossary ............................................................... 62 from lpm3 or lpm4 .............................................. 32 12 mechanical, packaging, and orderable 9.19 crystal oscillator, xt1, low-frequency mode .... 33 information .......................................................... 62 5 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes february 2014 * initial release. copyright ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 6 device characteristics table 1. family members (1) (2) flash ram comp_a+ adc10 usci_a0, package device bsl eem timer_a clock i/o (kb) (b) channel channel usci_b0 type lf, 24 28-tssop msp430g2553 1 1 16 512 2x ta3 8 8 1 dco, 16 20-tssop vlo lf, 24 28-tssop msp430g2453 1 1 8 512 2x ta3 8 8 1 dco, 16 20-tssop vlo (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . (2) package drawings, thermal data, and symbolization are available at www.ti.com/packaging . 4 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 7 terminal configuration and functions 7.1 20-pin pw package (top view) note: the pulldown resistors of port p3 should be enabled by setting p3ren.x = 1. 7.2 28-pin pw package (top view) copyright ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: msp430g2553-q1 MSP430G2453-Q1 pw28 (top view) 1 dvcc 2 p1.0/ta0clk/aclk/a0/ca0 3 4 5 p1.3/adc10clk/caout/vref-/veref-/a3/ca3 6 7 8 p3.0/ta0.2 9 p3.1/ta1.0 10 p2.0/ta1.0 19 p3.5/ta0.1 20 p3.6/ta0.2 21 p3.7/ta1clk/caout 22 23 24 rst/nmi/sbwtdio 25 test/sbwtck 26 xout/p2.7 27 xin/p2.6/ta0.1 28 dvss p1.6/ta0.1/ ca6/tdi/tclk uc b0somi/ucb0scl/a6/ p1.7/caout /a7/ca7/tdo/tdi / ucb0simo/ucb0sda p1.1/ta0.0/ a1/ca1 / uca0rxd/uca0somi p1.2/ta0.1/ a2/ca2 / uca0txd/uca0simo p1.4/smclk/ ca4/tck /vref+/veref+/a4/ ucb0ste/uca0clk p1.5/ta0.0/ a5/ca5/tms / ucb0clk/uca0ste 11 12 p2.2/ta1.1 13 p3.2/ta1.1 14 p3.3/ta1.2 15 p3.4/ta0.0 16 p2.3/ta1.0 17 p2.4/ta1.2 18 p2.5/ta1.2 p2.1/ta1.1 pw20 (top view) 1 dvcc 2 p1.0/ta0clk/aclk/a0/ca0 3 4 5 p1.3/adc10clk/caout/vref-/veref-/a3/ca3 6 7 8 p2.0/ta1.0 9 p2.1/ta1.1 10 p2.2/ta1.1 11 p2.3/ta1.0 12 p2.4/ta1.2 13 p2.5/ta1.2 14 15 16 rst/nmi/sbwtdio 17 test/sbwtck 18 xout/p2.7 19 xin/p2.6/ta0.1 20 dvss p1.6/ta0.1/ ca6/tdi/tclk uc b0somi/ucb0scl/a6/ p1.7/caout /a7/ca7/tdo/tdi / ucb0simo/ucb0sda p1.1/ta0.0/ a1/ca1 / uca0rxd/uca0somi p1.2/ta0.1/ a2/ca2 / uca0txd/uca0simo p1.4/smclk/ ca4/tck /vref+/veref+/a4/ ucb0ste/uca0clk p1.5/ta0.0/ a5/ca5/tms / ucb0clk/uca0ste
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 7.3 terminal functions table 2. terminal functions terminal no. i/o description name pw20 pw28 p1.0/ general-purpose digital i/o pin ta0clk/ timer0_a, clock signal taclk input aclk/ 2 2 i/o aclk signal output a0 adc10 analog input a0 ca0 comparator_a+, ca0 input p1.1/ general-purpose digital i/o pin ta0.0/ timer0_a, capture: cci0a input, compare: out0 output / bsl transmit uca0rxd/ usci_a0 uart mode: receive data input 3 3 i/o uca0somi/ usci_a0 spi mode: slave data out/master in a1/ adc10 analog input a1 ca1 comparator_a+, ca1 input p1.2/ general-purpose digital i/o pin ta0.1/ timer0_a, capture: cci1a input, compare: out1 output uca0txd/ usci_a0 uart mode: transmit data output 4 4 i/o uca0simo/ usci_a0 spi mode: slave data in/master out a2/ adc10 analog input a2 ca2 comparator_a+, ca2 input p1.3/ general-purpose digital i/o pin adc10clk/ adc10, conversion clock output a3/ adc10 analog input a3 5 5 i/o vref-/veref-/ adc10 negative reference voltage ca3/ comparator_a+, ca3 input caout comparator_a+, output p1.4/ general-purpose digital i/o pin smclk/ smclk signal output ucb0ste/ usci_b0 slave transmit enable uca0clk/ usci_a0 clock input/output 6 6 i/o a4/ adc10 analog input a4 vref+/veref+/ adc10 positive reference voltage ca4/ comparator_a+, ca4 input tck jtag test clock, input terminal for device programming and test p1.5/ general-purpose digital i/o pin ta0.0/ timer0_a, compare: out0 output / bsl receive ucb0clk/ usci_b0 clock input/output uca0ste/ 7 7 i/o usci_a0 slave transmit enable a5/ adc10 analog input a5 ca5/ comparator_a+, ca5 input tms jtag test mode select, input terminal for device programming and test 6 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 terminal functions (continued) table 2. terminal functions (continued) terminal no. i/o description name pw20 pw28 p1.6/ general-purpose digital i/o pin ta0.1/ timer0_a, compare: out1 output a6/ adc10 analog input a6 ca6/ 14 22 i/o comparator_a+, ca6 input ucb0somi/ usci_b0 spi mode: slave out master in ucb0scl/ usci_b0 i 2 c mode: scl i 2 c clock tdi/tclk jtag test data input or test clock input during programming and test p1.7/ general-purpose digital i/o pin a7/ adc10 analog input a7 ca7/ comparator_a+, ca7 input caout/ 15 23 i/o comparator_a+, output ucb0simo/ usci_b0 spi mode: slave in master out ucb0sda/ usci_b0 i 2 c mode: sda i 2 c data tdo/tdi jtag test data output terminal or test data input during programming and test p2.0/ general-purpose digital i/o pin 8 10 i/o ta1.0 timer1_a, capture: cci0a input, compare: out0 output p2.1/ general-purpose digital i/o pin 9 11 i/o ta1.1 timer1_a, capture: cci1a input, compare: out1 output p2.2/ general-purpose digital i/o pin 10 12 i/o ta1.1 timer1_a, capture: cci1b input, compare: out1 output p2.3/ general-purpose digital i/o pin 11 16 i/o ta1.0 timer1_a, capture: cci0b input, compare: out0 output p2.4/ general-purpose digital i/o pin 12 17 i/o ta1.2 timer1_a, capture: cci2a input, compare: out2 output p2.5/ general-purpose digital i/o pin 13 18 i/o ta1.2 timer1_a, capture: cci2b input, compare: out2 output xin/ input terminal of crystal oscillator p2.6/ 19 27 i/o general-purpose digital i/o pin ta0.1 timer0_a, compare: out1 output xout/ output terminal of crystal oscillator (1) 18 26 i/o p2.7 general-purpose digital i/o pin p3.0/ general-purpose digital i/o pin - 9 i/o ta0.2 timer0_a, capture: cci2a input, compare: out2 output p3.1/ general-purpose digital i/o pin - 8 i/o ta1.0 timer1_a, compare: out0 output p3.2/ general-purpose digital i/o pin - 13 i/o ta1.1 timer1_a, compare: out1 output p3.3/ general-purpose digital i/o - 14 i/o ta1.2 timer1_a, compare: out2 output p3.4/ general-purpose digital i/o - 15 i/o ta0.0 timer0_a, compare: out0 output (1) if xout/p2.7 is used as an input, excess current flows until p2sel.7 is cleared. this is due to the oscillator output driver connection to this pad after reset. copyright ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com terminal functions (continued) table 2. terminal functions (continued) terminal no. i/o description name pw20 pw28 p3.5/ general-purpose digital i/o - 19 i/o ta0.1 timer0_a, compare: out1 output p3.6/ general-purpose digital i/o - 20 i/o ta0.2 timer0_a, compare: out2 output p3.7/ general-purpose digital i/o ta1clk/ - 21 i/o timer1_a, clock signal taclk input caout comparator_a+, output rst/ reset nmi/ 16 24 i nonmaskable interrupt input sbwtdio spy-bi-wire test data input/output during programming and test test/ selects test mode for jtag pins on port 1. the device protection fuse is connected to test. 17 25 i sbwtck spy-bi-wire test clock input during programming and test avcc na na na analog supply voltage dvcc 1 1 na digital supply voltage dvss 20 28 na ground reference nc na na na not connected qfn pad na na na qfn package pad. connection to vss is recommended. 8 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 8 detailed description 8.1 cpu the msp430 cpu has a 16-bit risc architecture instruction set (continued) that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to- register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. the remaining registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses, and can be handled with all instructions. the instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. each instruction can operate on word and byte data. 8.2 instruction set the instruction set consists of 51 instructions with three formats and seven address modes. each instruction can operate on word and byte data. table 3 shows examples of the three types of instruction formats; table 4 shows the address modes. table 3. instruction word formats instruction format example operation dual operands, source-destination add r4,r5 r4 + r5 --- > r5 single operands, destination only call r8 pc -- > (tos), r8-- > pc relative jump, un/conditional jne jump-on-equal bit = 0 table 4. address mode descriptions (1) address mode s d syntax example operation register ? ? mov rs,rd mov r10,r11 r10 -- -- > r11 indexed ? ? mov x(rn),y(rm) mov 2(r5),6(r6) m(2+r5) -- -- > m(6+r6) symbolic (pc relative) ? ? mov ede,toni m(ede) -- -- > m(toni) absolute ? ? mov & mem, & tcdat m(mem) -- -- > m(tcdat) indirect ? mov @rn,y(rm) mov @r10,tab(r6) m(r10) -- -- > m(tab+r6) m(r10) -- -- > r11 indirect autoincrement ? mov @rn+,rm mov @r10+,r11 r10 + 2-- -- > r10 immediate ? mov #x,toni mov #45,toni #45 -- -- > m(toni) (1) s = source, d = destination copyright ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: msp430g2553-q1 MSP430G2453-Q1 program counter pc/r0 stack pointer sp/r1 status register sr/cg1/r2 constant generator cg2/r3 general-purpose register r4 general-purpose register r5 general-purpose register r6 general-purpose register r7 general-purpose register r8 general-purpose register r9 general-purpose register r10 general-purpose register r11 general-purpose register r12 general-purpose register r13 general-purpose register r15 general-purpose register r14
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 8.3 operating modes the msp430 has one active mode and five software selectable low-power modes of operation. an interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. the following six operating modes can be configured by software: ? active mode (am) ? all clocks are active ? low-power mode 0 (lpm0) ? cpu is disabled ? aclk and smclk remain active, mclk is disabled ? low-power mode 1 (lpm1) ? cpu is disabled ? aclk and smclk remain active, mclk is disabled ? dco's dc generator is disabled if dco not used in active mode ? low-power mode 2 (lpm2) ? cpu is disabled ? mclk and smclk are disabled ? dco's dc generator remains enabled ? aclk remains active ? low-power mode 3 (lpm3) ? cpu is disabled ? mclk and smclk are disabled ? dco's dc generator is disabled ? aclk remains active ? low-power mode 4 (lpm4) ? cpu is disabled ? aclk is disabled ? mclk and smclk are disabled ? dco's dc generator is disabled ? crystal oscillator is stopped 10 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 8.4 interrupt vector addresses the interrupt vectors and the power-up starting address are located in the address range 0ffffh to 0ffc0h. the vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. if the reset vector (located at address 0fffeh) contains 0ffffh (for example, flash is not programmed), the cpu goes into lpm4 immediately after power-up. table 5. interrupt sources, flags, and vectors system word interrupt source interrupt flag priority interrupt address power-up porifg external reset rstifg watchdog timer+ wdtifg reset 0fffeh 31, highest flash key violation keyv (2) pc out-of-range (1) nmi nmiifg (non)-maskable oscillator fault ofifg (non)-maskable 0fffch 30 flash memory access violation accvifg (2) (3) (non)-maskable timer1_a3 ta1ccr0 ccifg (4) maskable 0fffah 29 timer1_a3 ta1ccr2 ta1ccr1 ccifg, maskable 0fff8h 28 taifg (2) (4) comparator_a+ caifg (4) maskable 0fff6h 27 watchdog timer+ wdtifg maskable 0fff4h 26 timer0_a3 ta0ccr0 ccifg (4) maskable 0fff2h 25 timer0_a3 ta0ccr2 ta0ccr1 ccifg, taifg maskable 0fff0h 24 (5) (4) usci_a0/usci_b0 receive uca0rxifg, ucb0rxifg (2) (5) maskable 0ffeeh 23 usci_b0 i 2 c status usci_a0/usci_b0 transmit uca0txifg, ucb0txifg (2) (6) maskable 0ffech 22 usci_b0 i 2 c receive/transmit adc10 adc10ifg (4) maskable 0ffeah 21 (msp430g2x53 only) 0ffe8h 20 i/o port p2 (up to eight flags) p2ifg.0 to p2ifg.7 (2) (4) maskable 0ffe6h 19 i/o port p1 (up to eight flags) p1ifg.0 to p1ifg.7 (2) (4) maskable 0ffe4h 18 0ffe2h 17 0ffe0h 16 see (7) 0ffdeh 15 see (8) 0ffdeh to 14 to 0, lowest 0ffc0h (1) a reset is generated if the cpu tries to fetch instructions from within the module register memory address range (0h to 01ffh) or from within unused address ranges. (2) multiple source flags (3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. (4) interrupt flags are located in the module. (5) in spi mode: ucb0rxifg. in i 2 c mode: ucalifg, ucnackifg, icsttifg, ucstpifg. (6) in uart or spi mode: ucb0txifg. in i 2 c mode: ucb0rxifg, ucb0txifg. (7) this location is used as bootstrap loader security key (bslskey). a 0xaa55 at this location disables the bsl completely. a zero (0h) disables the erasure of the flash if an invalid password is supplied. (8) the interrupt vectors at addresses 0ffdeh to 0ffc0h are not used in this device and can be used for regular program code if necessary. copyright ? 2014, texas instruments incorporated submit documentation feedback 11 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 8.5 special function registers (sfrs) most interrupt and module enable bits are collected into the lowest address space. special function register bits not allocated to a functional purpose are not physically present in the device. simple software access is provided with this arrangement. legend rw: bit can be read and written. rw-0,1: bit can be read and written. it is reset or set by puc. rw-(0,1): bit can be read and written. it is reset or set by por. sfr bit is not present in device. table 6. interrupt enable register 1 and 2 address 7 6 5 4 3 2 1 0 00h accvie nmiie ofie wdtie rw-0 rw-0 rw-0 rw-0 wdtie watchdog timer interrupt enable. inactive if watchdog mode is selected. active if watchdog timer is configured in interval timer mode. ofie oscillator fault interrupt enable nmiie (non)maskable interrupt enable accvie flash access violation interrupt enable address 7 6 5 4 3 2 1 0 01h ucb0txie ucb0rxie uca0txie uca0rxie rw-0 rw-0 rw-0 rw-0 uca0rxie usci_a0 receive interrupt enable uca0txie usci_a0 transmit interrupt enable ucb0rxie usci_b0 receive interrupt enable ucb0txie usci_b0 transmit interrupt enable table 7. interrupt flag register 1 and 2 address 7 6 5 4 3 2 1 0 02h nmiifg rstifg porifg ofifg wdtifg rw-0 rw-(0) rw-(1) rw-1 rw-(0) wdtifg set on watchdog timer overflow (in watchdog mode) or security key violation. reset on v cc power-on or a reset condition at the rst/nmi pin in reset mode. ofifg flag set on oscillator fault. porifg power-on reset interrupt flag. set on v cc power-up. rstifg external reset interrupt flag. set on a reset condition at rst/nmi pin in reset mode. reset on v cc power-up. nmiifg set via rst/nmi pin address 7 6 5 4 3 2 1 0 03h ucb0txifg ucb0rxifg uca0txifg uca0rxifg rw-1 rw-0 rw-1 rw-0 uca0rxifg usci_a0 receive interrupt flag uca0txifg usci_a0 transmit interrupt flag ucb0rxifg usci_b0 receive interrupt flag ucb0txifg usci_b0 transmit interrupt flag 12 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 8.6 memory organization table 8. memory organization msp430g2453 msp430g2553 memory size 8kb 16kb main: interrupt vector flash 0xffff to 0xffc0 0xffff to 0xffc0 main: code memory flash 0xffff to 0xe000 0xffff to 0xc000 information memory size 256 byte 256 byte flash 010ffh to 01000h 010ffh to 01000h ram size 512 byte 512 byte 0x03ff to 0x0200 0x03ff to 0x0200 peripherals 16-bit 01ffh to 0100h 01ffh to 0100h 8-bit 0ffh to 010h 0ffh to 010h 8-bit sfr 0fh to 00h 0fh to 00h 8.7 bootstrap loader (bsl) the msp430 bsl enables users to program the flash memory or ram using a uart serial interface. access to the msp430 memory via the bsl is protected by user-defined password. for complete description of the features of the bsl and its implementation, see the msp430 programming via the bootstrap loader user's guide ( slau319 ). table 9. bsl function pins bsl function 20-pin pw package 28-pin pw package data transmit 3 - p1.1 3 - p1.1 data receive 7 - p1.5 7 - p1.5 8.8 flash memory the flash memory can be programmed via the spy-bi-wire/jtag port or in-system by the cpu. the cpu can perform single-byte and single-word writes to the flash memory. features of the flash memory include: ? flash memory has n segments of main memory and four segments of information memory (a to d) of 64 bytes each. each segment in main memory is 512 bytes in size. ? segments 0 to n may be erased in one step, or each segment may be individually erased. ? segments a to d can be erased individually or as a group with segments 0 to n. segments a to d are also called information memory . ? segment a contains calibration data. after reset segment a is protected against programming and erasing. it can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required. copyright ? 2014, texas instruments incorporated submit documentation feedback 13 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 8.9 peripherals peripherals are connected to the cpu through data, address, and control buses and can be handled using all instructions. for complete module descriptions, see the msp430x2xx family user's guide ( slau144 ). 8.9.1 oscillator and system clock the clock system is supported by the basic clock module that includes support for a 32768-hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (dco). the basic clock module is designed to meet the requirements of both low system cost and low power consumption. the internal dco provides a fast turn-on clock source and stabilizes in less than 1 s. the basic clock module provides the following clock signals: ? auxiliary clock (aclk), sourced either from a 32768-hz watch crystal or the internal lf oscillator. ? main clock (mclk), the system clock used by the cpu. ? sub-main clock (smclk), the sub-system clock used by the peripheral modules. the dco settings to calibrate the dco output frequency are stored in the information memory segment a. 8.9.2 main dco characteristics ? all ranges selected by rselx overlap with rselx + 1: rselx = 0 overlaps rselx = 1, ... rselx = 14 overlaps rselx = 15. ? dco control bits dcox have a step size as defined by parameter s dco . ? modulation control bits modx select how often f dco(rsel,dco+1) is used within the period of 32 dcoclk cycles. the frequency f dco(rsel,dco) is used for the remaining cycles. the frequency is an average equal to: 14 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1 dco(rsel,dco+1) dco(rsel,dco) average dco(rsel,dco) dco(rsel,dco+1) 32 f f f = mod f + (32 C mod) f
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 peripherals (continued) 8.9.3 calibration data stored in information memory segment a calibration data is stored for both the dco and for adc10 organized in a tag-length-value structure. table 10. tags used by the adc calibration tags name address value description tag_dco_30 0x10f6 0x01 dco frequency calibration at v cc = 3 v and t a = 30 c at calibration tag_adc10_1 0x10da 0x10 adc10_1 calibration tag tag_empty - 0xfe identifier for empty memory areas table 11. labels used by the adc calibration tags address label size condition at calibration and description offset cal_adc_25t85 0x0010 word inchx = 0x1010, ref2_5 = 1, t a = 85 c cal_adc_25t30 0x000e word inchx = 0x1010, ref2_5 = 1, t a = 30 c cal_adc_25vref_factor 0x000c word ref2_5 = 1, t a = 30 c, i vref+ = 1 ma cal_adc_15t85 0x000a word inchx = 0x1010, ref2_5 = 0, t a = 85 c cal_adc_15t30 0x0008 word inchx = 0x1010, ref2_5 = 0, t a = 30 c cal_adc_15vref_factor 0x0006 word ref2_5 = 0, t a = 30 c, i vref+ = 0.5 ma cal_adc_offset 0x0004 word external vref = 1.5 v, f adc10clk = 5 mhz cal_adc_gain_factor 0x0002 word external vref = 1.5 v, f adc10clk = 5 mhz cal_bc1_1mhz 0x0009 byte - cal_dco_1mhz 0x0008 byte - cal_bc1_8mhz 0x0007 byte - cal_dco_8mhz 0x0006 byte - cal_bc1_12mhz 0x0005 byte - cal_dco_12mhz 0x0004 byte - cal_bc1_16mhz 0x0003 byte - cal_dco_16mhz 0x0002 byte - 8.9.4 brownout the brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. 8.9.5 digital i/o up to three 8-bit i/o ports are implemented: ? all individual i/o bits are independently programmable. ? any combination of input, output, and interrupt condition (port p1 and port p2 only) is possible. ? edge-selectable interrupt input capability for all bits of port p1 and port p2 (if available). ? read/write access to port-control registers is supported by all instructions. ? each i/o has an individually programmable pullup or pulldown resistor. ? each i/o has an individually programmable pin oscillator enable bit to enable low-cost capacitive touch detection. 8.9.6 watchdog timer (wdt+) the primary function of the watchdog timer (wdt+) module is to perform a controlled system restart after a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. copyright ? 2014, texas instruments incorporated submit documentation feedback 15 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 8.9.7 timer_a3 (ta0, ta1) timer0/1_a3 is a 16-bit timer/counter with three capture/compare registers. timer_a3 can support multiple capture/compares, pwm outputs, and interval timing. timer_a3 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. table 12. timer0_a3 signal connections input pin number module output pin number device input module module output signal input name block pw20 pw28 pw20 pw28 signal p1.0-2 p1.0-2 taclk taclk aclk aclk timer na smclk smclk pinosc pinosc taclk inclk p1.1-3 p1.1-3 ta0.0 cci0a p1.1-3 p1.1-3 aclk cci0b p1.5-7 p1.5-7 ccr0 ta0 v ss gnd p3.4-15 v cc v cc p1.2-4 p1.2-4 ta0.1 cci1a p1.2-4 p1.2-4 caout cci1b p1.6-14 p1.6-22 ccr1 ta1 v ss gnd p2.6-19 p2.6-27 v cc v cc p3.5-19 p3.0-9 ta0.2 cci2a p3.0-9 pinosc pinosc ta0.2 cci2b p3.6-20 ccr2 ta2 v ss gnd v cc v cc table 13. timer1_a3 signal connections input pin number module output pin number device input module module output signal input name block pw20 pw28 pw20 pw28 signal - p3.7-21 taclk taclk aclk aclk timer na smclk smclk - p3.7-21 taclk inclk p2.0-8 p2.0-10 ta1.0 cci0a p2.0-8 p2.0-10 p2.3-11 p2.3-16 ta1.0 cci0b p2.3-11 p2.3-16 ccr0 ta0 v ss gnd p3.1-8 v cc v cc p2.1-9 p2.1-11 ta1.1 cci1a p2.1-9 p2.1-11 p2.2-10 p2.2-12 ta1.1 cci1b p2.2-10 p2.2-12 ccr1 ta1 v ss gnd p3.2-13 v cc v cc p2.4-12 p2.4-17 ta1.2 cci2a p2.4-12 p2.4-17 p2.5-13 p2.5-18 ta1.2 cci2b p2.5-13 p2.5-18 ccr2 ta2 v ss gnd p3.3-14 v cc v cc 16 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 8.9.8 universal serial communications interface (usci) the usci module is used for serial data communication. the usci module supports synchronous communication protocols such as spi (3 or 4 pin) and i 2 c, and asynchronous communication protocols such as uart, enhanced uart with automatic baudrate detection (lin), and irda. not all packages support the usci functionality. usci_a0 provides support for spi (3 or 4 pin), uart, enhanced uart, and irda. usci_b0 provides support for spi (3 or 4 pin) and i 2 c. 8.9.9 comparator_a+ the primary function of the comparator_a+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. 8.9.10 adc10 the adc10 module supports fast 10-bit analog-to-digital conversions. the module implements a 10-bit sar core, sample select control, reference generator, and data transfer controller (dtc) for automatic conversion result handling, allowing adc samples to be converted and stored without any cpu intervention. copyright ? 2014, texas instruments incorporated submit documentation feedback 17 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 8.9.11 peripheral file map table 14. peripherals with word access register module register description offset name adc10 adc data transfer start address adc10sa 1bch adc memory adc10mem 1b4h adc control register 1 adc10ctl1 1b2h adc control register 0 adc10ctl0 1b0h timer1_a3 capture/compare register ta1ccr2 0196h capture/compare register ta1ccr1 0194h capture/compare register ta1ccr0 0192h timer_a register ta1r 0190h capture/compare control ta1cctl2 0186h capture/compare control ta1cctl1 0184h capture/compare control ta1cctl0 0182h timer_a control ta1ctl 0180h timer_a interrupt vector ta1iv 011eh timer0_a3 capture/compare register ta0ccr2 0176h capture/compare register ta0ccr1 0174h capture/compare register ta0ccr0 0172h timer_a register ta0r 0170h capture/compare control ta0cctl2 0166h capture/compare control ta0cctl1 0164h capture/compare control ta0cctl0 0162h timer_a control ta0ctl 0160h timer_a interrupt vector ta0iv 012eh flash memory flash control 3 fctl3 012ch flash control 2 fctl2 012ah flash control 1 fctl1 0128h watchdog timer+ watchdog/timer control wdtctl 0120h 18 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 table 15. peripherals with byte access register module register description offset name usci_b0 usci_b0 transmit buffer ucb0txbuf 06fh usci_b0 receive buffer ucb0rxbuf 06eh usci_b0 status ucb0stat 06dh usci b0 i 2 c interrupt enable ucb0cie 06ch usci_b0 bit rate control 1 ucb0br1 06bh usci_b0 bit rate control 0 ucb0br0 06ah usci_b0 control 1 ucb0ctl1 069h usci_b0 control 0 ucb0ctl0 068h usci_b0 i 2 c slave address ucb0sa 011ah usci_b0 i 2 c own address ucb0oa 0118h usci_a0 usci_a0 transmit buffer uca0txbuf 067h usci_a0 receive buffer uca0rxbuf 066h usci_a0 status uca0stat 065h usci_a0 modulation control uca0mctl 064h usci_a0 baud rate control 1 uca0br1 063h usci_a0 baud rate control 0 uca0br0 062h usci_a0 control 1 uca0ctl1 061h usci_a0 control 0 uca0ctl0 060h usci_a0 irda receive control uca0irrctl 05fh usci_a0 irda transmit control uca0irtctl 05eh usci_a0 auto baud rate control uca0abctl 05dh adc10 adc analog enable 0 adc10ae0 04ah adc analog enable 1 adc10ae1 04bh adc data transfer control register 1 adc10dtc1 049h adc data transfer control register 0 adc10dtc0 048h comparator_a+ comparator_a+ port disable capd 05bh comparator_a+ control 2 cactl2 05ah comparator_a+ control 1 cactl1 059h basic clock system+ basic clock system control 3 bcsctl3 053h basic clock system control 2 bcsctl2 058h basic clock system control 1 bcsctl1 057h dco clock frequency control dcoctl 056h port p3 port p3 selection 2. pin p3sel2 043h (28-pin pw only) port p3 resistor enable p3ren 010h port p3 selection p3sel 01bh port p3 direction p3dir 01ah port p3 output p3out 019h port p3 input p3in 018h port p2 port p2 selection 2 p2sel2 042h port p2 resistor enable p2ren 02fh port p2 selection p2sel 02eh port p2 interrupt enable p2ie 02dh port p2 interrupt edge select p2ies 02ch port p2 interrupt flag p2ifg 02bh port p2 direction p2dir 02ah port p2 output p2out 029h port p2 input p2in 028h copyright ? 2014, texas instruments incorporated submit documentation feedback 19 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com table 15. peripherals with byte access (continued) register module register description offset name port p1 port p1 selection 2 p1sel2 041h port p1 resistor enable p1ren 027h port p1 selection p1sel 026h port p1 interrupt enable p1ie 025h port p1 interrupt edge select p1ies 024h port p1 interrupt flag p1ifg 023h port p1 direction p1dir 022h port p1 output p1out 021h port p1 input p1in 020h special function sfr interrupt flag 2 ifg2 003h sfr interrupt flag 1 ifg1 002h sfr interrupt enable 2 ie2 001h sfr interrupt enable 1 ie1 000h 20 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 9 specifications 9.1 absolute maximum ratings (1) voltage applied at v cc to v ss ? 0.3 v to 4.1 v voltage applied to any pin (2) ? 0.3 v to v cc + 0.3 v diode current at any device pin 2 ma unprogrammed device ? 55 c to 150 c storage temperature range, t stg (3) programmed device ? 55 c to 150 c (1) stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operating conditions " is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages referenced to v ss . the jtag fuse-blow voltage, v fb , is allowed to exceed the absolute maximum rating. the voltage is applied to the test pin when blowing the jtag fuse. (3) higher temperature may be applied during board soldering according to the current jedec j-std-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 9.2 recommended operating conditions typical values are specified at v cc = 3.3 v and t a = 25 c (unless otherwise noted) min nom max unit during program execution 1.8 3.6 v cc supply voltage v during flash programming 2.2 3.6 or erase v ss supply voltage 0 v t a operating free-air temperature i version ? 40 85 c v cc = 1.8 v, dc 6 duty cycle = 50% 10% v cc = 2.7 v, f system processor frequency (maximum mclk frequency) (1) (2) dc 12 mhz duty cycle = 50% 10% v cc = 3.3 v, dc 16 duty cycle = 50% 10% (1) the msp430 cpu is clocked directly with mclk. both the high and low phase of mclk must not exceed the pulse duration of the specified maximum frequency. (2) modules might have a different maximum input clock specification. see the specification of the respective module in this data sheet. note: minimum processor frequency is defined by system clock. flash program or erase operations require a minimum v cc of 2.2 v. figure 2. safe operating area copyright ? 2014, texas instruments incorporated submit documentation feedback 21 product folder links: msp430g2553-q1 MSP430G2453-Q1 supply voltage range, during flash memory programming supply voltage range, during program execution legend : 16 mhz system frequency - mhz 12 mhz 6 mhz 1.8 v supply voltage - v 3.3 v 2.7 v 2.2 v 3.6 v
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 9.3 active mode supply current into v cc excluding external current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) parameter test conditions t a v cc min typ max unit f dco = f mclk = f smclk = 1 mhz, 2.2 v 230 f aclk = 0 hz, program executes in flash, active mode (am) i am,1mhz bcsctl1 = calbc1_1mhz, a current at 1 mhz 3 v 330 420 dcoctl = caldco_1mhz, cpuoff = 0, scg0 = 0, scg1 = 0, oscoff = 0 (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) the currents are characterized with a micro crystal cc4v-t1a smd crystal with a load capacitance of 9 pf. the internal and external load capacitance is chosen to closely match the required 9 pf. 9.4 typical characteristics, active mode supply current (into v cc ) figure 3. active mode current vs v cc , t a = 25 c figure 4. active mode current vs dco frequency 22 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1 0.0 1.0 2.0 3.0 4.0 5.0 1.5 2.0 2.5 3.0 3.5 4.0 v cc ? supply voltage ? v active mode current ? ma f dco = 1 mhz f dco = 8 mhz f dco = 12 mhz f dco = 16 mhz 0.0 1.0 2.0 3.0 4.0 0.0 4.0 8.0 12.0 16.0 f dco ? dco frequency ? mhz active mode current ? ma t a = 25 c t a = 85 c v cc = 2.2 v v cc = 3 v t a = 25 c t a = 85 c
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 9.5 low-power mode supply currents (into v cc ) excluding external current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) parameter test conditions t a v cc min typ max unit f mclk = 0 mhz, f smclk = f dco = 1 mhz, f aclk = 32768 hz, low-power mode 0 i lpm0,1mhz bcsctl1 = calbc1_1mhz, 25 c 2.2 v 56 a (lpm0) current (3) dcoctl = caldco_1mhz, cpuoff = 1, scg0 = 0, scg1 = 0, oscoff = 0 f mclk = f smclk = 0 mhz, f dco = 1 mhz, f aclk = 32768 hz, low-power mode 2 i lpm2 bcsctl1 = calbc1_1mhz, 25 c 2.2 v 22 a (lpm2) current (4) dcoctl = caldco_1mhz, cpuoff = 1, scg0 = 0, scg1 = 1, oscoff = 0 f dco = f mclk = f smclk = 0 mhz, low-power mode 3 f aclk = 32768 hz, i lpm3,lfxt1 25 c 2.2 v 0.7 1.5 a (lpm3) current (4) cpuoff = 1, scg0 = 1, scg1 = 1, oscoff = 0 f dco = f mclk = f smclk = 0 mhz, low-power mode 3 f aclk from internal lf oscillator (vlo), i lpm3,vlo 25 c 2.2 v 0.5 0.7 a current, (lpm3) (4) cpuoff = 1, scg0 = 1, scg1 = 1, oscoff = 0 f dco = f mclk = f smclk = 0 mhz, 25 c 0.1 0.5 low-power mode 4 f aclk = 0 hz, i lpm4 2.2 v a (lpm4) current (5) cpuoff = 1, scg0 = 1, scg1 = 1, 85 c 0.8 1.7 oscoff = 1 (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) the currents are characterized with a micro crystal cc4v-t1a smd crystal with a load capacitance of 9 pf. the internal and external load capacitance is chosen to closely match the required 9 pf. (3) current for brownout and wdt clocked by smclk included. (4) current for brownout and wdt clocked by aclk included. (5) current for brownout included. copyright ? 2014, texas instruments incorporated submit documentation feedback 23 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 9.6 typical characteristics, low-power mode supply currents over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) figure 6. lpm4 current vs temperature figure 5. lpm3 current vs temperature 24 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 -40 i C low-power mode current C a lpm3 vcc = 3.6 v t C temperature C c a vcc = 1.8 v vcc = 3 v vcc = 2.2 v -20 0 20 40 60 80 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 -40 i C low-power mode current C a lpm4 vcc = 3.6 v t C temperature C c a vcc = 1.8 v vcc = 3 v vcc = 2.2 v -20 0 20 40 60 80
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 9.7 schmitt-trigger inputs, ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit 0.45 v cc 0.75 v cc v it+ positive-going input threshold voltage v 3 v 1.35 2.25 0.25 v cc 0.55 v cc v it ? negative-going input threshold voltage v 3 v 0.75 1.65 v hys input voltage hysteresis (v it+ ? v it ? ) 3 v 0.3 1 v for pullup: v in = v ss r pull pullup/pulldown resistor 3 v 20 35 50 k ? for pulldown: v in = v cc c i input capacitance v in = v ss or v cc 5 pf 9.8 leakage current, ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit i lkg(px.y) high-impedance leakage current (1) (2) 3 v 50 na (1) the leakage current is measured with v ss or v cc applied to the corresponding pin(s), unless otherwise noted. (2) the leakage of the digital port pins is measured individually. the port pin is selected for input and the pullup/pulldown resistor is disabled. 9.9 outputs, ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v oh high-level output voltage i (ohmax) = ? 6 ma (1) 3 v v cc ? 0.3 v v ol low-level output voltage i (olmax) = 6 ma (1) 3 v v ss + 0.3 v (1) the maximum total current, i (ohmax) and i (olmax) , for all outputs combined should not exceed 48 ma to hold the maximum voltage drop specified. 9.10 output frequency, ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit port output frequency f px.y px.y, c l = 20 pf, r l = 1 k (1) (2) 3 v 12 mhz (with load) f port_clk clock output frequency px.y, c l = 20 pf (2) 3 v 16 mhz (1) a resistive divider with two 0.5-k resistors between v cc and v ss is used as load. the output is connected to the center tap of the divider. (2) the output voltage reaches at least 10% and 90% v cc at the specified toggle frequency. copyright ? 2014, texas instruments incorporated submit documentation feedback 25 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 9.11 typical characteristics, outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) figure 7. typical low-level output current vs low-level figure 8. typical low-level output current vs low-level output voltage output voltage figure 9. typical high-level output current vs high-level figure 10. typical high-level output current vs high-level output voltage output voltage 26 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1 v oh ? high-level output voltage ? v ?25 ?20 ?15 ?10 ?5 0 0 0.5 1 1.5 2 2.5 v cc = 2.2 v p1.7 t a = 25c t a = 85c oh i ? typical high-level output current ? ma v oh ? high-level output voltage ? v ?50 ?40 ?30 ?20 ?10 0 0 0.5 1 1.5 2 2.5 3 3.5 v cc = 3 v p1.7 t a = 25c t a = 85c oh i ? typical high-level output current ? ma v ol ? low-level output voltage ? v 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 v cc = 2.2 v p1.7 t a = 25c t a = 85c ol i ? typical low-level output current ? ma v ol ? low-level output voltage ? v 0 10 20 30 40 50 0 0.5 1 1.5 2 2.5 3 3.5 v cc = 3 v p1.7 t a = 25c t a = 85c ol i ? typical low-level output current ? ma
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 9.12 pin-oscillator frequency ? ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit p1.y, c l = 10 pf, r l = 100 k (1) (2) 1400 fo p1.x port output oscillation frequency 3 v khz p1.y, c l = 20 pf, r l = 100 k (1) (2) 900 p2.0 to p2.5, c l = 10 pf, r l = 100 k (1) (2) 1800 fo p2.x port output oscillation frequency khz p2.0 to p2.5, c l = 20 pf, r l = 100 k (1) (2) 3 v 1000 p2.6 and p2.7, c l = 20 pf, r l = 100 fo p2.6/7 port output oscillation frequency 3 v 700 khz k (1) (2) p3.y, c l = 10 pf, r l = 100 k (1) (2) 1800 fo p3.x port output oscillation frequency khz p3.y, c l = 20 pf, r l = 100 k (1) (2) 1000 (1) a resistive divider with two 50-k resistors between v cc and v ss is used as load. the output is connected to the center tap of the divider. (2) the output voltage reaches at least 10% and 90% v cc at the specified toggle frequency. 9.13 typical characteristics, pin-oscillator frequency one output active at a time. one output active at a time. figure 11. typical oscillating frequency vs load figure 12. typical oscillating frequency vs load capacitance capacitance copyright ? 2014, texas instruments incorporated submit documentation feedback 27 product folder links: msp430g2553-q1 MSP430G2453-Q1 c load ? external capacitance ? pf 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 10 50 100 p1.y p2.0 ... p2.5 p2.6, p2.7 v cc = 3.0 v fosc ? typical oscillation frequency ? mhz c load ? external capacitance ? pf 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 10 50 100 p1.y p2.0 ... p2.5 p2.6, p2.7 v cc = 2.2 v fosc ? typical oscillation frequency ? mhz
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 9.14 por, bor (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit 0.7 v cc(start) see figure 13 dv cc /dt 3 v/s v v (b_it--) v (b_it ? ) see figure 13 through figure 15 dv cc /dt 3 v/s 1.35 v v hys(b_it ? ) see figure 13 dv cc /dt 3 v/s 140 mv t d(bor) see figure 13 2000 s pulse duration needed at rst/nmi pin to t (reset) 2.2 v 2 s accepted reset internally (1) the current consumption of the brownout module is already included in the i cc current consumption data. the voltage level v (b_it ? ) + v hys(b_it ? ) is 1.8 v. (2) during power up, the cpu begins code execution following a period of t d(bor) after v cc = v (b_it ? ) + v hys(b_it ? ) . the default dco settings must not be changed until v cc v cc(min) , where v cc(min) is the minimum supply voltage for the desired operating frequency. figure 13. por and bor vs supply voltage figure 14. v cc(drop) level with a square voltage drop to generate a por or bor signal 28 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1 v cc(drop) v cc 3 v t pw 0 0.5 1 1.5 2 0.001 1 1000 typical conditions 1 ns 1 ns t pw ? pulse width ? s v cc(drop) ? v t pw ? pulse width ? s v cc = 3 v 0 1 t d(bor) v cc v (b_it?) v hys(b_it?) v cc(start)
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 figure 15. v cc(drop) level with a triangle voltage drop to generate a por or bor signal copyright ? 2014, texas instruments incorporated submit documentation feedback 29 product folder links: msp430g2553-q1 MSP430G2453-Q1 v cc 0 0.5 1 1.5 2 v cc(drop) t pw t pw ? pulse width ? s v cc(drop) ? v 3 v 0.001 1 1000 t f t r t pw ? pulse width ? s t f = t r typical conditions v cc = 3 v
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 9.15 dco frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit rselx < 14 1.8 3.6 v cc supply voltage rselx = 14 2.2 3.6 v rselx = 15 3 3.6 f dco(0,0) dco frequency (0, 0) rselx = 0, dcox = 0, modx = 0 3 v 0.06 0.14 mhz f dco(0,3) dco frequency (0, 3) rselx = 0, dcox = 3, modx = 0 3 v 0.07 0.17 mhz f dco(1,3) dco frequency (1, 3) rselx = 1, dcox = 3, modx = 0 3 v 0.15 mhz f dco(2,3) dco frequency (2, 3) rselx = 2, dcox = 3, modx = 0 3 v 0.21 mhz f dco(3,3) dco frequency (3, 3) rselx = 3, dcox = 3, modx = 0 3 v 0.30 mhz f dco(4,3) dco frequency (4, 3) rselx = 4, dcox = 3, modx = 0 3 v 0.41 mhz f dco(5,3) dco frequency (5, 3) rselx = 5, dcox = 3, modx = 0 3 v 0.58 mhz f dco(6,3) dco frequency (6, 3) rselx = 6, dcox = 3, modx = 0 3 v 0.54 1.06 mhz f dco(7,3) dco frequency (7, 3) rselx = 7, dcox = 3, modx = 0 3 v 0.80 1.50 mhz f dco(8,3) dco frequency (8, 3) rselx = 8, dcox = 3, modx = 0 3 v 1.6 mhz f dco(9,3) dco frequency (9, 3) rselx = 9, dcox = 3, modx = 0 3 v 2.3 mhz f dco(10,3) dco frequency (10, 3) rselx = 10, dcox = 3, modx = 0 3 v 3.4 mhz f dco(11,3) dco frequency (11, 3) rselx = 11, dcox = 3, modx = 0 3 v 4.25 mhz f dco(12,3) dco frequency (12, 3) rselx = 12, dcox = 3, modx = 0 3 v 4.30 7.30 mhz f dco(13,3) dco frequency (13, 3) rselx = 13, dcox = 3, modx = 0 3 v 6.00 7.8 9.60 mhz f dco(14,3) dco frequency (14, 3) rselx = 14, dcox = 3, modx = 0 3 v 8.60 13.9 mhz f dco(15,3) dco frequency (15, 3) rselx = 15, dcox = 3, modx = 0 3 v 12.0 18.5 mhz f dco(15,7) dco frequency (15, 7) rselx = 15, dcox = 7, modx = 0 3 v 16.0 26.0 mhz frequency step between s rsel s rsel = f dco(rsel+1,dco) /f dco(rsel,dco) 3 v 1.35 ratio range rsel and rsel+1 frequency step between s dco s dco = f dco(rsel,dco+1) /f dco(rsel,dco) 3 v 1.08 ratio tap dco and dco+1 duty cycle measured at smclk output 3 v 50 % 30 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 9.16 calibrated dco frequencies, tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions t a v cc min typ max unit bcsctl1 = calbc1_1mhz, 1-mhz tolerance over dcoctl = caldco_1mhz, 0 c to 85 c 3 v -3 0.5 +3 % temperature (1) calibrated at 30 c and 3 v bcsctl1 = calbc1_1mhz, 1-mhz tolerance over v cc dcoctl = caldco_1mhz, 30 c 1.8 v to 3.6 v -3 2 +3 % calibrated at 30 c and 3 v bcsctl1 = calbc1_1mhz, 1-mhz tolerance overall dcoctl = caldco_1mhz, -40 c to 85 c 1.8 v to 3.6 v -6 3 +6 % calibrated at 30 c and 3 v bcsctl1 = calbc1_8mhz, 8-mhz tolerance over dcoctl = caldco_8mhz, 0 c to 85 c 3 v -3 0.5 +3 % temperature (1) calibrated at 30 c and 3 v bcsctl1 = calbc1_8mhz, 8-mhz tolerance over v cc dcoctl = caldco_8mhz, 30 c 2.2 v to 3.6 v -3 2 +3 % calibrated at 30 c and 3 v bcsctl1 = calbc1_8mhz, 8-mhz tolerance overall dcoctl = caldco_8mhz, -40 c to 85 c 2.2 v to 3.6 v -6 3 +6 % calibrated at 30 c and 3 v bcsctl1 = calbc1_12mhz, 12-mhz tolerance over dcoctl = caldco_12mhz, 0 c to 85 c 3 v -3 0.5 +3 % temperature (1) calibrated at 30 c and 3 v bcsctl1 = calbc1_12mhz, 12-mhz tolerance over v cc dcoctl = caldco_12mhz, 30 c 2.7 v to 3.6 v -3 2 +3 % calibrated at 30 c and 3 v bcsctl1 = calbc1_12mhz, 12-mhz tolerance overall dcoctl = caldco_12mhz, -40 c to 85 c 2.7 v to 3.6 v -6 3 +6 % calibrated at 30 c and 3 v bcsctl1 = calbc1_16mhz, 16-mhz tolerance over dcoctl = caldco_16mhz, 0 c to 85 c 3 v -3 0.5 +3 % temperature (1) calibrated at 30 c and 3 v bcsctl1 = calbc1_16mhz, 16-mhz tolerance over v cc dcoctl = caldco_16mhz, 30 c 3.3 v to 3.6 v -3 2 +3 % calibrated at 30 c and 3 v bcsctl1 = calbc1_16mhz, 16-mhz tolerance overall dcoctl = caldco_16mhz, -40 c to 85 c 3.3 v to 3.6 v -6 3 +6 % calibrated at 30 c and 3 v (1) this is the frequency change from the measured frequency at 30 c over temperature. copyright ? 2014, texas instruments incorporated submit documentation feedback 31 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 9.17 wakeup from lower-power modes (lpm3 or lpm4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit dco clock wake-up time from lpm3 bcsctl1 = calbc1_1mhz, t dco,lpm3/4 3 v 1.5 s or lpm4 (1) dcoctl = caldco_1mhz cpu wake-up time from lpm3 or 1/f mclk + t cpu,lpm3/4 lpm4 (2) t clock,lpm3/4 (1) the dco clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge observable externally on a clock pin (mclk or smclk). (2) parameter applicable only if dcoclk is used for mclk. 9.18 typical characteristics, dco clock wakeup time from lpm3 or lpm4 figure 16. dco wakeup time from lpm3 vs dco frequency 32 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1 dco frequency ? mhz 0.10 1.00 10.00 0.10 1.00 10.00 dco wake time ? s rselx = 0...11 rselx = 12...15
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 9.19 crystal oscillator, xt1, low-frequency mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit lfxt1 oscillator crystal f lfxt1,lf xts = 0, lfxt1sx = 0 or 1 1.8 v to 3.6 v 32768 hz frequency, lf mode 0, 1 lfxt1 oscillator logic level f lfxt1,lf,logic square wave input frequency, xts = 0, xcapx = 0, lfxt1sx = 3 1.8 v to 3.6 v 10000 32768 50000 hz lf mode xts = 0, lfxt1sx = 0, 500 f lfxt1,lf = 32768 hz, c l,eff = 6 pf oscillation allowance for oa lf k ? lf crystals xts = 0, lfxt1sx = 0, 200 f lfxt1,lf = 32768 hz, c l,eff = 12 pf xts = 0, xcapx = 0 1 xts = 0, xcapx = 1 5.5 integrated effective load c l,eff pf capacitance, lf mode (2) xts = 0, xcapx = 2 8.5 xts = 0, xcapx = 3 11 xts = 0, measured at p2.0/aclk, duty cycle, lf mode 2.2 v 30 50 70 % f lfxt1,lf = 32768 hz oscillator fault frequency, f fault,lf xts = 0, xcapx = 0, lfxt1sx = 3 (4) 2.2 v 10 10000 hz lf mode (3) (1) to improve emi on the xt1 oscillator, the following guidelines should be observed. ( a) keep the trace between the device and the crystal as short as possible. ( b) design a good ground plane around the oscillator pins. ( c) prevent crosstalk from other clock or data lines into oscillator pins xin and xout. ( d) avoid running pcb traces underneath or adjacent to the xin and xout pins. ( e) use assembly materials and processes that avoid any parasitic load on the oscillator xin and xout pins. ( f) if a conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. ( g) do not route the xout line to the jtag header to support the serial programming adapter as shown in other documentation. this signal is no longer required for the serial programming adapter. (2) includes parasitic bond and package capacitance (approximately 2 pf per pin). because the pcb adds additional capacitance, it is recommended to verify the correct load by measuring the aclk frequency. for a correct setup, the effective load capacitance should always match the specification of the used crystal. (3) frequencies below the min specification set the fault flag. frequencies above the max specification do not set the fault flag. frequencies in between might set the flag. (4) measured with logic-level input frequency but also applies to operation with crystals. 9.20 internal very-low-power low-frequency oscillator (vlo) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter t a v cc min typ max unit f vlo vlo frequency -40 c to 85 c 3 v 4 12 20 khz df vlo /d t vlo frequency temperature drift -40 c to 85 c 3 v 0.5 %/ c df vlo /dv cc vlo frequency supply voltage drift 25 c 1.8 v to 3.6 v 4 %/v 9.21 timer_a over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit f ta timer_a input clock frequency smclk, duty cycle = 50% 10% f system mhz t ta,cap timer_a capture timing ta0, ta1 3 v 20 ns copyright ? 2014, texas instruments incorporated submit documentation feedback 33 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 9.22 usci (uart mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit f usci usci input clock frequency smclk, duty cycle = 50% 10% f system mhz maximum bitclk clock frequency f max,bitclk 3 v 2 mhz (equals baudrate in mbaud) (1) t uart receive deglitch time (2) 3 v 50 100 600 ns (1) the dco wake-up time must be considered in lpm3 and lpm4 for baud rates above 1 mhz. (2) pulses on the uart receive input (ucxrx) shorter than the uart receive deglitch time are suppressed. to ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. 9.23 usci (spi master mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 17 and figure 18 ) parameter test conditions v cc min typ max unit f usci usci input clock frequency smclk, duty cycle = 50% 10% f system mhz t su,mi somi input data setup time 3 v 75 ns t hd,mi somi input data hold time 3 v 0 ns t valid,mo simo output data valid time uclk edge to simo valid, c l = 20 pf 3 v 20 ns figure 17. spi master mode, ckph = 0 figure 18. spi master mode, ckph = 1 34 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1 t su,mi t hd,mi uclk somi simo t valid,mo ckpl = 0 ckpl = 1 1/f ucxclk t hd,mo t lo/hi t lo/hi t su,mi t hd,mi uclk somi simo t valid,mo t hd,mo ckpl = 0 ckpl = 1 t lo/hi t lo/hi 1/f ucxclk
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 9.24 usci (spi slave mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 19 and figure 20 ) parameter test conditions v cc min typ max unit t ste,lead ste lead time, ste low to clock 3 v 50 ns t ste,lag ste lag time, last clock to ste high 3 v 10 ns t ste,acc ste access time, ste low to somi data out 3 v 50 ns ste disable time, ste high to somi high t ste,dis 3 v 50 ns impedance t su,si simo input data setup time 3 v 15 ns t hd,si simo input data hold time 3 v 10 ns uclk edge to somi valid, t valid,so somi output data valid time 3 v 50 75 ns c l = 20 pf figure 19. spi slave mode, ckph = 0 figure 20. spi slave mode, ckph = 1 copyright ? 2014, texas instruments incorporated submit documentation feedback 35 product folder links: msp430g2553-q1 MSP430G2453-Q1 ste uclk ckpl = 0 ckpl = 1 somi simo t su,si t hd,si t valid,so t ste,lead 1/f ucxclk t ste,lag t ste,dis t ste,acc t hd,mo t lo/hi t lo/hi ste uclk ckpl = 0 ckpl = 1 somi simo t su,si t hd,si t valid,so t ste,lead 1/f ucxclk t lo/hi t lo/hi t ste,lag t ste,dis t ste,acc t hd,so
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 9.25 usci (i 2 c mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 21 ) parameter test conditions v cc min typ max unit f usci usci input clock frequency smclk, duty cycle = 50% 10% f system mhz f scl scl clock frequency 3 v 0 400 khz f scl 100 khz 4.0 t hd,sta hold time (repeated) start 3 v s f scl > 100 khz 0.6 f scl 100 khz 4.7 t su,sta setup time for a repeated start 3 v s f scl > 100 khz 0.6 t hd,dat data hold time 3 v 0 ns t su,dat data setup time 3 v 250 ns t su,sto setup time for stop 3 v 4.0 s pulse width of spikes suppressed by t sp 3 v 50 100 600 ns input filter figure 21. i 2 c mode timing 9.26 comparator_a+ over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit i (dd) (1) caon = 1, carsel = 0, caref = 0 3 v 45 a caon = 1, carsel = 0, i (refladder/ caref = 1, 2, or 3, 3 v 45 a refdiode) no load at ca0 and ca1 v (ic) common ? mode input voltage caon = 1 3 v 0 v cc -1 v pca0 = 1, carsel = 1, caref = 1, v (ref025) (voltage at 0.25 v cc node) / v cc 3 v 0.24 no load at ca0 and ca1 pca0 = 1, carsel = 1, caref = 2, v (ref050) (voltage at 0.5 v cc node) / v cc 3 v 0.48 no load at ca0 and ca1 pca0 = 1, carsel = 1, caref = 3, v (refvt) see figure 22 and figure 23 3 v 490 mv no load at ca0 and ca1, ta = 85 c v (offset) offset voltage (2) 3 v 10 mv v hys input hysteresis caon = 1 3 v 0.7 mv t a = 25 c, overdrive 10 mv, 120 ns without filter: caf = 0 response time t (response) 3 v (low-high and high-low) t a = 25 c, overdrive 10 mv, 1.5 s with filter: caf = 1 (1) the leakage current for the comparator_a+ terminals is identical to i lkg(px.y) specification. (2) the input offset voltage can be cancelled by using the caex bit to invert the comparator_a+ inputs on successive measurements. the two successive measurements are then summed together. 36 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1 sda scl t hd,dat t su,dat t hd,sta t high t low t buf t hd,sta t su,sta t sp t su,sto
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 9.27 typical characteristics ? comparator_a+ figure 22. v (refvt) vs temperature, v cc = 3 v figure 23. v (refvt) vs temperature, v cc = 2.2 v figure 24. short resistance vs v in /v cc copyright ? 2014, texas instruments incorporated submit documentation feedback 37 product folder links: msp430g2553-q1 MSP430G2453-Q1 400 450 500 550 600 650 v = 2.2 v cc typical t C free-air temperature C c a v C reference voltage C mv (refvt) -45 -25 -5 15 35 55 75 95 115 v /v C normalized input voltage C v/v in cc 1 10 100 0 short resistance C k w v = 1.8 v cc v = 3.6 v cc v = 2.2 v cc v = 3 v cc 0.2 0.4 0.6 0.8 1 t C free-air temperature C c a 400 450 500 550 600 650 v = 3 v cc v C reference voltage C mv (refvt) typical -45 -25 -5 15 35 55 75 95 115
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 9.28 10-bit adc, power supply and input range conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions t a v cc min typ max unit v cc analog supply voltage v ss = 0 v 2.2 3.6 v all ax terminals, analog inputs v ax analog input voltage (2) 3 v 0 v cc v selected in adc10ae register f adc10clk = 5.0 mhz, adc10on = 1, refon = 0, i adc10 adc10 supply current (3) 25 c 3 v 0.6 ma adc10sht0 = 1, adc10sht1 = 0, adc10div = 0 f adc10clk = 5.0 mhz, adc10on = 0, ref2_5v = 0, 0.25 refon = 1, refout = 0 reference supply current, i ref+ 25 c 3 v ma reference buffer disabled (4) f adc10clk = 5.0 mhz, adc10on = 0, ref2_5v = 1, 0.25 refon = 1, refout = 0 f adc10clk = 5.0 mhz, reference buffer supply adc10on = 0, refon = 1, i refb,0 25 c 3 v 1.1 ma current with adc10sr = 0 (4) ref2_5v = 0, refout = 1, adc10sr = 0 f adc10clk = 5.0 mhz, reference buffer supply adc10on = 0, refon = 1, i refb,1 25 c 3 v 0.5 ma current with adc10sr = 1 (4) ref2_5v = 0, refout = 1, adc10sr = 1 only one terminal ax can be selected c i input capacitance 25 c 3 v 27 pf at one time r i input mux on resistance 0 v v ax v cc 25 c 3 v 1000 ? (1) the leakage current is defined in the leakage current table with px.y/ax parameter. (2) the analog input voltage range must be within the selected reference voltage range v r+ to v r ? for valid conversion results. (3) the internal reference supply current is not included in current consumption parameter i adc10 . (4) the internal reference current is supplied via terminal v cc . consumption is independent of the adc10on control bit, unless a conversion is active. the refon bit enables the built-in reference to settle before starting an a/d conversion. 38 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 9.29 10-bit adc, built-in voltage reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit i vref+ 1 ma, ref2_5v = 0 2.2 positive built-in reference v cc,ref+ v analog supply voltage range i vref+ 1 ma, ref2_5v = 1 2.9 i vref+ i vref+ max, ref2_5v = 0 1.41 1.5 1.59 positive built-in reference v ref+ 3 v v voltage i vref+ i vref+ max, ref2_5v = 1 2.35 2.5 2.65 maximum vref+ load i ld,vref+ 3 v 1 ma current i vref+ = 500 a 100 a, analog input voltage v ax ? 0.75 v, 2 ref2_5v = 0 vref+ load regulation 3 v lsb i vref+ = 500 a 100 a, analog input voltage v ax ? 1.25 v, 2 ref2_5v = 1 i vref+ = 100 a 900 a, v ref+ load regulation v ax ? 0.5 vref+, 3 v 400 ns response time error of conversion result 1 lsb, adc10sr = 0 maximum capacitance at c vref+ i vref+ 1 ma, refon = 1, refout = 1 3 v 100 pf pin vref+ ppm/ tc ref+ temperature coefficient (1) i vref+ = const with 0 ma i vref+ 1 ma 3 v 100 c settling time of internal i vref+ = 0.5 ma, ref2_5v = 0, t refon reference voltage to 99.9% 3.6 v 30 s refon = 0 1 vref i vref+ = 0.5 ma, settling time of reference t refburst ref2_5v = 1, refon = 1, 3 v 2 s buffer to 99.9% vref refburst = 1, adc10sr = 0 (1) calculated using the box method: (max(-40 to 85 c) ? min(-40 to 85 c)) / min(-40 to 85 c) / (85 c ? ( ? 40 c)) copyright ? 2014, texas instruments incorporated submit documentation feedback 39 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 9.30 10-bit adc, external reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit veref+ > veref ? , 1.4 v cc sref1 = 1, sref0 = 0 positive external reference input veref+ v voltage range (2) veref ? veref+ v cc ? 0.15 v, 1.4 3 sref1 = 1, sref0 = 1 (3) negative external reference input veref ? veref+ > veref ? 0 1.2 v voltage range (4) differential external reference veref input voltage range, veref+ > veref ? (5) 1.4 v cc v veref = veref+ ? veref ? 0 v veref+ v cc , 3 v 1 sref1 = 1, sref0 = 0 i veref+ static input current into veref+ a 0 v veref+ v cc ? 0.15 v 3 v, 3 v 0 sref1 = 1, sref0 = 1 (3) i veref ? static input current into veref ? 0 v veref ? v cc 3 v 1 a (1) the external reference is used during conversion to charge and discharge the capacitance array. the input capacitance, c i , is also the dynamic load for an external reference during conversion. the dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. (2) the accuracy limits the minimum positive external reference voltage. lower reference voltage levels may be applied with reduced accuracy requirements. (3) under this condition the external reference is internally buffered. the reference buffer is active and requires the reference buffer supply current i refb . the current consumption can be limited to the sample and conversion period with reburst = 1. (4) the accuracy limits the maximum negative external reference voltage. higher reference voltage levels may be applied with reduced accuracy requirements. (5) the accuracy limits the minimum external differential reference voltage. lower differential reference voltage levels may be applied with reduced accuracy requirements. 9.31 10-bit adc, timing parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit adc10sr = 0 0.45 6.3 adc10 input clock for specified performance of f adc10clk 3 v mhz frequency adc10 linearity parameters adc10sr = 1 0.45 1.5 adc10 built-in oscillator adc10divx = 0, adc10sselx = 0, f adc10osc 3 v 3.7 6.3 mhz frequency f adc10clk = f adc10osc adc10 built-in oscillator, adc10sselx = 0, 3 v 2.06 3.51 f adc10clk = f adc10osc t convert conversion time s 13 f adc10clk from aclk, mclk, or smclk: adc10div adc10sselx 0 1/f adc10clk turn-on settling time of t adc10on (1) 100 ns the adc (1) the condition is that the error in a conversion started after t adc10on is less than 0.5 lsb. the reference and input signal are already settled. 9.32 10-bit adc, linearity parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit e i integral linearity error 3 v 1 lsb e d differential linearity error 3 v 1 lsb e o offset error source impedance r s < 100 ? 3 v 1 lsb e g gain error 3 v 1.1 2 lsb e t total unadjusted error 3 v 2 5 lsb 40 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 9.33 10-bit adc, temperature sensor and built-in v mid over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit temperature sensor supply refon = 0, inchx = 0ah, i sensor 3 v 60 a current (1) t a = 25 c tc sensor adc10on = 1, inchx = 0ah (2) 3 v 3.55 mv/ c sample time required if channel adc10on = 1, inchx = 0ah, t sensor(sample) 3 v 30 s 10 is selected (3) error of conversion result 1 lsb i vmid current into divider at channel 11 adc10on = 1, inchx = 0bh 3 v (4) a adc10on = 1, inchx = 0bh, v mid v cc divider at channel 11 3 v 1.5 v v mid ? 0.5 v cc sample time required if channel adc10on = 1, inchx = 0bh, t vmid(sample) 3 v 1220 ns 11 is selected (5) error of conversion result 1 lsb (1) the sensor current i sensor is consumed if (adc10on = 1 and refon = 1) or (adc10on = 1 and inch = 0ah and sample signal is high). when refon = 1, i sensor is included in i ref+ . when refon = 0, i sensor applies during conversion of the temperature sensor input (inch = 0ah). (2) the following formula can be used to calculate the temperature sensor output voltage: v sensor,typ = tc sensor (273 + t [ c] ) + v offset,sensor [mv] or v sensor,typ = tc sensor t [ c] + v sensor (t a = 0 c) [mv] (3) the typical equivalent impedance of the sensor is 51 k ? . the sample time required includes the sensor-on time t sensor(on) . (4) no additional current is needed. the v mid is used during sampling. (5) the on-time t vmid(on) is included in the sampling time t vmid(sample) ; no additional on time is needed. 9.34 flash memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test v cc min typ max unit conditions v cc(pgm/erase) program and erase supply voltage 2.2 3.6 v f ftg flash timing generator frequency 257 476 khz i pgm supply current from v cc during program 2.2 v, 3.6 v 1 5 ma i erase supply current from v cc during erase 2.2 v, 3.6 v 1 7 ma t cpt cumulative program time (1) 2.2 v, 3.6 v 10 ms t cmerase cumulative mass erase time 2.2 v, 3.6 v 20 ms program/erase endurance 10 4 10 5 cycles t retention data retention duration t j = 25 c 100 years t word word or byte program time (2) 30 t ftg t block, 0 block program time for first byte or word (2) 25 t ftg block program time for each additional byte or t block, 1-63 (2) 18 t ftg word t block, end block program end-sequence wait time (2) 6 t ftg t mass erase mass erase time (2) 10593 t ftg t seg erase segment erase time (2) 4819 t ftg (1) the cumulative program time must not be exceeded when writing to a 64-byte flash block. this parameter applies to all programming methods: individual word write, individual byte write, and block write modes. (2) these values are hardwired into the flash controller ' s state machine (t ftg = 1/f ftg ). copyright ? 2014, texas instruments incorporated submit documentation feedback 41 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 9.35 ram over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit v (ramh) ram retention supply voltage (1) cpu halted 1.6 v (1) this parameter defines the minimum supply voltage v cc when the data in ram remains unchanged. no program execution should happen during this supply voltage condition. 9.36 jtag and spy-bi-wire interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit f sbw spy-bi-wire input frequency 2.2 v 0 20 mhz t sbw,low spy-bi-wire low clock pulse duration 2.2 v 0.025 15 s spy-bi-wire enable time t sbw,en 2.2 v 1 s (test high to acceptance of first clock edge (1) ) t sbw,ret spy-bi-wire return to normal operation time 2.2 v 15 100 s f tck tck input frequency (2) 2.2 v 0 5 mhz r internal internal pulldown resistance on test 2.2 v 25 60 90 k ? (1) tools accessing the spy-bi-wire interface need to wait for the maximum t sbw,en time after pulling the test/sbwtck pin high before applying the first sbwtck clock edge. (2) f tck may be restricted to meet the timing requirements of the module selected. 9.37 jtag fuse (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit v cc(fb) supply voltage during fuse-blow condition t a = 25 c 2.5 v v fb voltage level on test for fuse blow 6 7 v i fb supply current into test during fuse blow 100 ma t fb time to blow fuse 1 ms (1) once the fuse is blown, no further access to the jtag/test, spy-bi-wire, and emulation feature is possible, and jtag is switched to bypass mode. 42 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 10 i/o port schematics 10.1 port p1 pin schematic: p1.0 to p1.2, input/output with schmitt trigger copyright ? 2014, texas instruments incorporated submit documentation feedback 43 product folder links: msp430g2553-q1 MSP430G2453-Q1 pxdir.y from timer p1.0/ta0clk/aclk/ a0/ca0 p1.1/ta0.0/uca0rxd/ uca0somi/a1/ca1 p1.2/ta0.1/uca0txd/ uca0simo/a2/ca2 from usci 1 to module from timer pxout.y dvss dvcc 1 tax.y taxclk bus keeper en 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxsel2.y 1 0 inchx = y to adc10 pxsel.y 1 3 2 1 0 pxsel2.y pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y direction0: input 1: output pxsel.y 3 2 1 0 pxsel2.y from comparator to comparator capd.y or adc10ae0.y 0
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com port p1 pin schematic: p1.0 to p1.2, input/output with schmitt trigger (continued) table 16. port p1 (p1.0 to p1.2) pin functions control bits and signals (1) pin name x function adc10ae.x (p1.x) p1dir.x p1sel.x p1sel2.x capd.y inch.x=1 p1.0/ p1.x (i/o) i: 0; o: 1 0 0 0 0 ta0clk/ ta0.taclk 0 1 0 0 0 aclk/ aclk 1 1 0 0 0 0 a0/ a0 x x x 1 (y = 0) 0 ca0/ ca0 x x x 0 1 (y = 0) pin osc capacitive sensing x 0 1 0 0 p1.1/ p1.x (i/o) i: 0; o: 1 0 0 0 0 ta0.0/ ta0.0 1 1 0 0 0 ta0.cci0a 0 1 0 0 0 uca0rxd/ uca0rxd from usci 1 1 0 0 1 uca0somi/ uca0somi from usci 1 1 0 0 a1/ a1 x x x 1 (y = 1) 0 ca1/ ca1 x x x 0 1 (y = 1) pin osc capacitive sensing x 0 1 0 0 p1.2/ p1.x (i/o) i: 0; o: 1 0 0 0 0 ta0.1/ ta0.1 1 1 0 0 0 ta0.cci1a 0 1 0 0 0 uca0txd/ uca0txd from usci 1 1 0 0 2 uca0simo/ uca0simo from usci 1 1 0 0 a2/ a2 x x x 1 (y = 2) 0 ca2/ ca2 x x x 0 1 (y = 2) pin osc capacitive sensing x 0 1 0 0 (1) x = don ' t care 44 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 10.2 port p1 pin schematic: p1.3, input/output with schmitt trigger copyright ? 2014, texas instruments incorporated submit documentation feedback 45 product folder links: msp430g2553-q1 MSP430G2453-Q1 p1.3/adc10clk/caout/ a3/vref-/veref-/ca3 direction0: input 1: output to module from adc10 pxout.y dvss dvcc 1 tax.y taxclk bus keeper en 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxdir.y 1 0,2,3 pxsel2.y pxsel.y 1 0 inchx = y from comparator to adc10 to comparator to adc10 vref- 1 0 vss sref2 pxsel.y 1 3 2 1 0 from comparator pxsel2.y pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y or adc10ae0.y capd.y pxsel2.y
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com port p1 pin schematic: p1.3, input/output with schmitt trigger (continued) table 17. port p1 (p1.3) pin functions control bits and signals (1) pin name x function adc10ae.x (p1.x) p1dir.x p1sel.x p1sel2.x capd.y inch.x=1 p1.3/ p1.x (i/o) i: 0; o: 1 0 0 0 0 adc10clk/ adc10clk 1 1 0 0 0 caout/ caout 1 1 1 0 0 a3/ a3 x x x 1 (y = 3) 0 3 vref-/ vref- x x x 1 0 veref-/ veref- x x x 1 0 ca3/ ca3 x x x 0 1 (y = 3) pin osc capacitive sensing x 0 1 0 0 (1) x = don ' t care 46 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 10.3 port p1 pin schematic: p1.4, input/output with schmitt trigger copyright ? 2014, texas instruments incorporated submit documentation feedback 47 product folder links: msp430g2553-q1 MSP430G2453-Q1 p1.4/smclk/ucb0ste/uca0clk/ vref+/veref+/ca4/tck a4/ direction0: input 1: output to module smclk pxout.y dvss dvcc 1 tax.y taxclk bus keeper en 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxdir.y 1 0 pxsel2.y pxsel.y 1 0 inchx = y from comparator to adc10 to comparator from/to adc10 ref+ pxsel.y 1 3 2 1 0 pxsel2.y from jtag to jtag pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y capd.y or adc10ae0.y from module
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com port p1 pin schematic: p1.4, input/output with schmitt trigger (continued) table 18. port p1 (p1.4) pin functions control bits and signals (1) pin name x function adc10ae.x (p1.x) p1dir.x p1sel.x p1sel2.x jtag mode capd.y inch.x=1 p1.4/ p1.x (i/o) i: 0; o: 1 0 0 0 0 0 smclk/ smclk 1 1 0 0 0 0 ucb0ste/ ucb0ste from usci 1 1 0 0 0 uca0clk/ uca0clk from usci 1 1 0 0 0 vref+/ vref+ x x x 1 0 0 4 veref+/ veref+ x x x 1 0 0 a4/ a4 x x x 1 (y = 4) 0 0 ca4 ca4 x x x 0 0 1 (y = 4) tck/ tck x x x 0 1 0 capacitive pin osc x 0 1 0 0 0 sensing (1) x = don ' t care 48 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 10.4 port p1 pin schematic: p1.5 to p1.7, input/output with schmitt trigger copyright ? 2014, texas instruments incorporated submit documentation feedback 49 product folder links: msp430g2553-q1 MSP430G2453-Q1 p1.5/ta0.0/ucb0clk/uca0ste/ a5/ca5/tms p1.6/ta0.1/ucb0somi/ucb0scl/ a6/ca6/tdi/tclk p1.7/caout/ucb0simo/ucb0sda/ a7/ca7/tdo/tdi from module from module to module from module pxout.y dvss dvcc 1 tax.y taxclk bus keeper en 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxsel2.y 1 0 inchx = y to adc10 pxsel.y 1 3 2 1 0 pxsel2.y from jtag to jtag pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y direction0: input 1: output pxdir.y from module pxsel.y 3 2 1 0 pxsel2.y adc10ae0.y from comparator to comparator capd.y
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com port p1 pin schematic: p1.5 to p1.7, input/output with schmitt trigger (continued) table 19. port p1 (p1.5 to p1.7) pin functions control bits and signals (1) pin name x function adc10ae.x (p1.x) p1dir.x p1sel.x p1sel2.x jtag mode capd.y inch.x=1 p1.5/ p1.x (i/o) i: 0; o: 1 0 0 0 0 0 ta0.0/ ta0.0 1 1 0 0 0 0 ucb0clk/ ucb0clk from usci 1 1 0 0 0 uca0ste/ uca0ste from usci 1 1 0 0 0 5 a5/ a5 x x x 1 (y = 5) 0 0 ca5 ca5 x x x 0 0 1 (y = 5) tms tms x x x 0 1 0 capacitive pin osc x 0 1 0 0 0 sensing p1.6/ p1.x (i/o) i: 0; o: 1 0 0 0 0 0 ta0.1/ ta0.1 1 1 0 0 0 0 ucb0somi/ ucb0somi from usci 1 1 0 0 0 ucb0scl/ ucb0scl from usci 1 1 0 0 0 6 a6/ a6 x x x 1 (y = 6) 0 0 ca6 ca6 x x x 0 0 1 (y = 6) tdi/tclk/ tdi/tclk x x x 0 1 0 capacitive pin osc x 0 1 0 0 0 sensing p1.7/ p1.x (i/o) i: 0; o: 1 0 0 0 0 0 ucb0simo/ ucb0simo from usci 1 1 0 0 0 ucb0sda/ ucb0sda from usci 1 1 0 0 0 a7/ a7 x x x 1 (y = 7) 0 0 7 ca7 ca7 x x x 0 0 1 (y = 7) caout caout 1 1 0 0 0 0 tdo/tdi/ tdo/tdi x x x 0 1 0 capacitive pin osc x 0 1 0 0 0 sensing (1) x = don ' t care 50 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 10.5 port p2 pin schematic: p2.0 to p2.5, input/output with schmitt trigger copyright ? 2014, texas instruments incorporated submit documentation feedback 51 product folder links: msp430g2553-q1 MSP430G2453-Q1 p2.0/ta1.0 p2.1/ta1.1 p2.2/ta1.1 p2.3/ta1.0 p2.4/ta1.2 p2.5/ta1.2 from timer direction0: input 1: output to module pxout.y dvss dvcc 1 tax.y taxclk 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxsel2.y 1 0 pxsel.y 1 3 2 1 0 pxsel2.y pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y pxdir.y 1 0 pxsel.y 0
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com port p2 pin schematic: p2.0 to p2.5, input/output with schmitt trigger (continued) table 20. port p2 (p2.0 to p2.5) pin functions control bits and signals (1) pin name x function (p2.x) p2dir.x p2sel.x p2sel2.x p2.0/ p2.x (i/o) i: 0; o: 1 0 0 ta1.0/ timer1_a3.cci0a 0 1 0 0 timer1_a3.ta0 1 1 0 pin osc capacitive sensing x 0 1 p2.1/ p2.x (i/o) i: 0; o: 1 0 0 ta1.1/ timer1_a3.cci1a 0 1 0 1 timer1_a3.ta1 1 1 0 pin osc capacitive sensing x 0 1 p2.2/ p2.x (i/o) i: 0; o: 1 0 0 ta1.1/ timer1_a3.cci1b 0 1 0 2 timer1_a3.ta1 1 1 0 pin osc capacitive sensing x 0 1 p2.3/ p2.x (i/o) i: 0; o: 1 0 0 ta1.0/ timer1_a3.cci0b 0 1 0 3 timer1_a3.ta0 1 1 0 pin osc capacitive sensing x 0 1 p2.4/ p2.x (i/o) i: 0; o: 1 0 0 ta1.2/ timer1_a3.cci2a 0 1 0 4 timer1_a3.ta2 1 1 0 pin osc capacitive sensing x 0 1 p2.5/ p2.x (i/o) i: 0; o: 1 0 0 ta1.2/ timer1_a3.cci2b 0 1 0 5 timer1_a3.ta2 1 1 0 pin osc capacitive sensing x 0 1 (1) x = don ' t care 52 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 10.6 port p2 pin schematic: p2.6, input/output with schmitt trigger copyright ? 2014, texas instruments incorporated submit documentation feedback 53 product folder links: msp430g2553-q1 MSP430G2453-Q1 xin/p2.6/ta0.1 direction0: input 1: output to module from module pxout.y dvss dvcc 1 tax.y taxclk 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxdir.y 1 0 pxsel2.y pxsel.y 1 0 pxsel.y 1 3 2 1 0 pxsel2.y pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y 1 0 xout/p2.7 lf off lfxt1clk pxsel.6 and pxsel.7 bcsctl3.lfxt1sx = 11
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com port p2 pin schematic: p2.6, input/output with schmitt trigger (continued) table 21. port p2 (p2.6) pin functions control bits and signals (1) pin name x function p2sel.6 p2sel2.6 (p2.x) p2dir.x p2sel.7 p2sel2.7 1 0 xin xin 0 1 0 0 0 p2.6 p2.x (i/o) i: 0; o: 1 x 0 6 1 0 ta0.1 timer0_a3.ta1 1 0 0 0 1 pin osc capacitive sensing x x x (1) x = don ' t care 54 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 10.7 port p2 pin schematic: p2.7, input/output with schmitt trigger copyright ? 2014, texas instruments incorporated submit documentation feedback 55 product folder links: msp430g2553-q1 MSP430G2453-Q1 xout/p2.7 direction0: input 1: output to module from module pxout.y dvss dvcc 1 tax.y taxclk 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxdir.y 1 0 pxsel2.y pxsel.y 1 0 pxsel.y 1 3 2 1 0 pxsel2.y pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y 1 0 xin lf off lfxt1clk pxsel.6 and pxsel.7 bcsctl3.lfxt1sx = 11 from p2.6
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com port p2 pin schematic: p2.7, input/output with schmitt trigger (continued) table 22. port p2 (p2.7) pin functions control bits and signals (1) pin name x function p2sel.6 p2sel2.6 (p2.x) p2dir.x p2sel.7 p2sel2.7 1 0 xout/ xout 1 1 0 0 0 p2.7/ 7 p2.x (i/o) i: 0; o: 1 x 0 0 1 pin osc capacitive sensing x x x (1) x = don ' t care 56 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 10.8 port p3 pin schematic: p3.0 to p3.7, input/output with schmitt trigger (28-pin pw and 32-pin rhb packages only) copyright ? 2014, texas instruments incorporated submit documentation feedback 57 product folder links: msp430g2553-q1 MSP430G2453-Q1 p3.0/ta0.2 p3.1/ta1.0 p3.2/ta1.1 p3.3/ta1.2 p3.4/ta0.0 p3.5/ta0.1 p3.6/ta0.2 p3.7/ta1clk/caout direction0: input 1: output to module from module pxout.y dvss dvcc 1 tax.y taxclk 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxdir.y 1 0 pxsel2.y pxsel.y 1 0 pxsel.y 1 3 2 1 0 pxsel2.y
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com port p3 pin schematic: p3.0 to p3.7, input/output with schmitt trigger (28-pin pw and 32-pin rhb packages only) (continued) table 23. port p3 (p3.0 to p3.7) pin functions (28-pin pw and 32-pin rhb packages only) control bits and signals (1) pin name x function (p3.x) p3dir.x p3sel.x p3sel2.x p3.0/ p3.x (i/o) i: 0; o: 1 0 0 ta0.2/ timer0_a3.cci2a 0 1 0 0 timer0_a3.ta2 1 1 0 pin osc capacitive sensing x 0 1 p3.1/ p3.x (i/o) i: 0; o: 1 0 0 ta1.0/ 1 timer1_a3.ta0 1 1 0 pin osc capacitive sensing x 0 1 p3.2/ p3.x (i/o) i: 0; o: 1 0 0 ta1.1/ 2 timer1_a3.ta1 1 1 0 pin osc capacitive sensing x 0 1 p3.3/ p3.x (i/o) i: 0; o: 1 0 0 ta1.2/ 3 timer1_a3.ta2 1 1 0 pin osc capacitive sensing x 0 1 p3.4/ p3.x (i/o) i: 0; o: 1 0 0 ta0.0/ 4 timer0_a3.ta0 1 1 0 pin osc capacitive sensing x 0 1 p3.5/ p3.x (i/o) i: 0; o: 1 0 0 ta0.1/ 5 timer0_a3.ta1 1 1 0 pin osc capacitive sensing x 0 1 p3.6/ p3.x (i/o) i: 0; o: 1 0 0 ta0.2/ 6 timer0_a3.ta2 1 1 0 pin osc capacitive sensing x 0 1 p3.7/ p3.x (i/o) i: 0; o: 1 0 0 ta1clk/ timer1_a3.taclk 0 1 0 7 caout/ comparator output 1 1 0 pin osc capacitive sensing x 0 1 (1) x = don ' t care 58 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 11 device and documentation support 11.1 device support 11.1.1 development tools support all msp430 ? microcontrollers are supported by a wide variety of software and hardware development tools. tools are available from ti and various third parties. see them all at www.ti.com/msp430tools . 11.1.1.1 hardware features see the code composer studio for msp430 user's guide ( slau157 ) for details on the available features. break- range lpmx.5 msp430 4-wire 2-wire clock state trace points break- debugging architecture jtag jtag control sequencer buffer (n) points support msp430 yes yes 2 no yes no no no 11.1.1.2 recommended hardware options 11.1.1.2.1 target socket boards the target socket boards allow easy programming and debugging of the device using jtag. they also feature header pin outs for prototyping. target socket boards are orderable individually or as a kit with the jtag programmer and debugger included. the following table shows the compatible target boards and the supported packages. package target board and programmer bundle target board only 28-pin tssop (pw) msp-fet430u28a msp-ts430pw28a 11.1.1.2.2 experimenter boards experimenter boards and evaluation kits are available for some msp430 devices. these kits feature additional hardware components and connectivity for full system evaluation and prototyping. see www.ti.com/msp430tools for details. 11.1.1.2.3 debugging and programming tools hardware programming and debugging tools are available from ti and from its third party suppliers. see the full list of available tools at www.ti.com/msp430tools . 11.1.1.2.4 production programmers the production programmers expedite loading firmware to devices by programming several devices simultaneously. part number pc port features provider msp-gang serial and usb program up to eight devices at a time. works with pc or standalone. texas instruments 11.1.1.3 recommended software options 11.1.1.3.1 integrated development environments software development tools are available from ti or from third parties. open source solutions are also available. this device is supported by code composer studio ? ide (ccs). 11.1.1.3.2 msp430ware msp430ware is a collection of code examples, data sheets, and other design resources for all msp430 devices delivered in a convenient package. msp430ware is available as a component of ccs or as a standalone package. copyright ? 2014, texas instruments incorporated submit documentation feedback 59 product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 11.1.1.3.3 command-line programmer msp430 flasher is an open-source, shell-based interface for programming msp430 microcontrollers through a fet programmer or ez430 using jtag or spy-bi-wire (sbw) communication. msp430 flasher can be used to download binary files (.txt or .hex) files directly to the msp430 flash without the need for an ide. 11.1.1.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e community ti's engineer-to-engineer (e2e) community . created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. ti embedded processors wiki texas instruments embedded processors wiki . established to help developers get started with embedded processors from texas instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 11.1.2 device and development tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all msp430 ? mcu devices and support tools. each msp430 ? mcu commercial family member has one of three prefixes: msp, pms, or xms (for example, msp430f5259). texas instruments recommends two of three possible prefix designators for its support tools: msp and mspx. these prefixes represent evolutionary stages of product development from engineering prototypes (with xms for devices and mspx for tools) through fully qualified production devices and tools (with msp for devices and msp for tools). device development evolutionary flow: xms ? experimental device that is not necessarily representative of the final device's electrical specifications pms ? final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification msp ? fully qualified production device support tool development evolutionary flow: mspx ? development-support product that has not yet completed texas instruments internal qualification testing. msp ? fully-qualified development-support product xms and pms devices and mspx development-support tools are shipped against the following disclaimer: "developmental product is intended for internal evaluation purposes." msp devices and msp development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. predictions show that prototype devices (xms and pms) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, pzp) and temperature range (for example, t). figure 25 provides a legend for reading the complete device name for any family member. 60 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
msp430g2553-q1 , MSP430G2453-Q1 www.ti.com slas966 ? march 2014 figure 25. device nomenclature copyright ? 2014, texas instruments incorporated submit documentation feedback 61 product folder links: msp430g2553-q1 MSP430G2453-Q1 processor family cc = embedded rf radio msp = mixed signal processor xms = experimental silicon pms = prototype device 430 mcu platform tis low power microcontroller platform device type memory type c = romf = flash fr = fram g = flash or fram (value line) l = no nonvolatile memory specialized application afe = analog front end bt = preprogrammed with bluetooth bq = contactless power cg = rom medical fe = flash energy meter fg = flash medical fw = flash electronic flow meter series 1 series = up to 8 mhz2 series = up to 16 mhz 3 series = legacy 4 series = up to 16 mhz w/ lcd 5 series = up to 25 mhz6 series = up to 25 mhz w/ lcd 0 = low voltage series feature set various levels of integration within a series optional: a = revision n/a optional: temperature range s = 0c to 50 c c to 70 c i = -40 c to 85 c t = -40 c to 105 c c = 0 packaging www.ti.com/packaging optional: tape and reel t = small reel (7 inch) r = large reel (11 inch) no markings = tube or tray optional: additional features -ep = enhanced product (-40c to 105c) -ht = extreme temperature parts (-55c to 150c) -q1 = automotive q100 qualified msp 430 f 5 438 a i zqw t xx processor family series optional: temperature range 430 mcu platform packaging device type optional: a = revision optional: tape and reel feature set optional: additional features
msp430g2553-q1 , MSP430G2453-Q1 slas966 ? march 2014 www.ti.com 11.2 documentation support 11.2.1 related documents the following documents describe the msp430g2x53 devices. copies of these documents are available on the internet at www.ti.com . slau144 msp430x2xx family user's guide. detailed information on the modules and peripherals available in this device family. slaz440 msp430g2553 device erratasheet. describes the known exceptions to the functional specifications for the msp430g2553 device. slaz437 msp430g2453 device erratasheet. describes the known exceptions to the functional specifications for the msp430g2453 device. 11.3 related links table 24 lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 24. related links technical tools & support & parts product folder sample & buy documents software community msp430g2553-q1 click here click here click here click here click here MSP430G2453-Q1 click here click here click here click here click here 11.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e community ti's engineer-to-engineer (e2e) community . created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. ti embedded processors wiki texas instruments embedded processors wiki . established to help developers get started with embedded processors from texas instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 11.5 trademarks msp430, code composer studio are trademarks of texas instruments. all other trademarks are the property of their respective owners. 11.6 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 62 submit documentation feedback copyright ? 2014, texas instruments incorporated product folder links: msp430g2553-q1 MSP430G2453-Q1
package option addendum www.ti.com 1-apr-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples msp430g2453ipw8rq1 active tssop pw 28 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 g2453q1 msp430g2553ipw8rq1 active tssop pw 28 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 g2553q1 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 1-apr-2014 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of MSP430G2453-Q1, msp430g2553-q1 : ? catalog: msp430g2453 , msp430g2553 note: qualified version definitions: ? catalog - ti's standard catalog product
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant msp430g2453ipw8rq1 tssop pw 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 q1 msp430g2553ipw8rq1 tssop pw 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 q1 package materials information www.ti.com 31-mar-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) msp430g2453ipw8rq1 tssop pw 28 2000 367.0 367.0 38.0 msp430g2553ipw8rq1 tssop pw 28 2000 367.0 367.0 38.0 package materials information www.ti.com 31-mar-2014 pack materials-page 2

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